Power Reduction in Superscalar Datapaths Through Dynamic Bit-Slice Activation

Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose
Procedings of Int'l. Workshop "Innovative Architecture for Future Generation High-Performance Processors and Systems" (IWIA'01), 2001, pp.16-24.

Abstract

We show by simulating the execution of SPEC 95 benchmarks on a true hardware-level, cycle-by-cycle simulator for a superscalar CPU that about half of the bytes of operands flowing on the datapath, particularly the leading bytes, are all zeros. Furthermore, a significant number of the bits within the non-zero part of the data flowing on the various paths within the processor do not change from their prior value. We show how these two facts, attesting to the lack of a high level entropy in the data streams, can be exploited to reduce power dissipation within all explicit and implicit storage components of a typical superscalar datapath such a register files, dispatch buffers, reorder buffers, as well as interconnections such as buses and direct links. Our simulation results and SPICE measurements from representative VLSI layouts show power savings of about 25% on the average over all SPEC 95 benchmarks.

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