Reducing Power Requirements of Instruction Scheduling Through Dynamic Allocation of Multiple Datapath Resources

Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose
Proceedings of the 34^th Int'l. Symposium on Microarchitecture (MICRO-34), Austin, TX, December 2001, pp.90-101.

Abstract

The "one-size-fits-all" philosophy used for permanently allocating datapath resources in today's superscalar CPUs to maximize performance across a wide range of applications results in the overcommitment of resources in general. To reduce power dissipation in the datapath, the resource allocations can be dynamically adjusted based on the demands of applications. We propose a mechanism to dynamically, simultaneously and independently adjust the sizes of the issue queue (IQ), the reorder buffer (ROB) and the load/store queue (LSQ) based on the periodic sampling of their occupancies to achieve significant power savings with minimal impact on performance. Resource upsizing is done more aggresively (compared to downsizing) using the relative rate of blocked dispatches to limit the performance penalty. Our results are valiudated by the execution of SPEC 95 benchmark suite on a substantially modified version of Simplescalar simulator, where the IQ, the ROB, the LSQ and the register files are implemented as seperate structures, as in the case with most practical implementations. For the SPEC 95 benchmarks, the use of our technique in a 4-way superscalar processor results in a power savings in excess of 70% within individual components and an average power savings of 53% for the IQ, LSQ and ROB combined for the entire benchmark suite with an average performance penalty of only 5%.

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