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YEDITEPE UNIVERSITY SEMINAR BLUE-CHIP Mine MESTA* 15/01/2010 Abstract Nowadays, all the systems, from high-performance servers to battery-operated handheld devices, aim reliability, high-performance and longevity. As it is directly related with these aims, the issue of energy/power reduction in processors is becoming more and more important. In this study, we aim to adapt a methodology for energy savings in the simultaneous multi-threaded (SMT) processors. The method aims resizing of datapath resources according to the demands of the running applications. To achieve this, the targeted resources are physically divided into multiple partitions, and turned on and off according to the needs of the applications. Since, the energy consumption of the turned-off datapath resources is quite low, as a result, it becomes possible to have great amount of energy savings within a processor. However, special care must be taken when there are multiple threads racing against each other to gain access to shared datapath resources. As a result, our proposed microarchitectural technique, named Blue-Chip, achieve 0.5% Instructions Per Cycle (IPC) and 3.2% Total number of instructions Per Cycle (TPC) improvement, while it turns off 45% of the Reorder Buffer (ROB), 59% of the Load-Store Queue (LSQ), 43% of the Issue Queue (IQ), 30% of the integer Physical Register Files (PRF) and, finally, 48% of the floating PRF, on the average across all simulated benchmarks. According to our estimates, the total processor power is reduced by 12%, on the average.
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