Sezer GÖREN UĞURDAĞ

Sezer Gören Uğurdağ
Professor


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Publications



Turk Y., Ozcan B., Gören S. "Precise Vehicle Positioning for Indoor Navigation via OpenXC", International Conference on Vehicle Technology and Intelligent Transport Systems (VEHITS’2018), Funchal, Portugal, 16-18 March, 2018.

Gök M.Y., Gören S., Unsalan C., Sagiroglu M.S. "Highly accurate and sensitive short read aligner," Turkish Journal of Electrical and Computer Sciences. (In Press 2018)



Yildiz A., Gursoy C.C., Gören S., "Fault Emulation on Heterogeneous Architectures", International Conference on Computer Science and Engineering (UBMK'2017), Antalya, 2017.

Turk Y., Gören S., "Gamified Self-Paced E-Learning Platform for Computer Science Courses", 9th International Conference ICT Innovations (ICT'2017), Skopje, Macedonia, 2017.

Ugurdag H.F., de Dinechin F., Gener Y.S., Gören S., Didier L.-S., "Hardware division by small integer constants," IEEE Transactions on Computers, 10.1109/TC.2017.2707488, 2017.

Kakacak A., Guzel A.E., Cihangir O., Gören S., Ugurdag H.F., "Fast Multiplier Generator for FPGAs with LUT based Partial Product Generation and Column/Row Compression," Integration, the VLSI Journal, 57, pp. 147-157, Elsevier, 2017.



Gursoy C.C., Yildiz A., Gören S., "On optimization of multi-cycle tests for test quality and application time," 14th IEEE East-West Design & Test Symposium (EWDTS'2016), Yerevan, Armenia, 2016.

Buyukmihci M., Levent V.E., Guzel A.E., Ates O., Tosun M., Akgun T., Erbas C., Gören S., Ugurdag H.F., "Output Domain Downscaler," International Symposium on Computer and Information Sciences (ISCIS'2016), Krakow, Poland, 2016.

Canbay F., Levent V.E., Serbes G., Ugurdag H.F., Gören S., Aydin N., "A Code Generator for Implementing Dual Tree Complex Wavelet Transform on Reconfigurable Architectures for Mobile Applications," Healthcare Technology Letters (IET), accepted.

Ugurdag H.F., Bayram A., Levent V.E., Gören S., "Efficient Combinational Circuits for Division by Small Integer Constants," 23rd IEEE Symposium on Computer Arithmetic (ARITH'2016), Santa Clara, CA, USA, 2016.

Canbay F., Levent V.E., Serbes G., Ugurdag, H.F., Gören S., Aydın N., "A Multi-channel Real Time Implementation of Dual Tree Complex Wavelet Transform in Field Programmable Gate Arrays," 14th Mediterranean Conference on Medical and Biological Engineering and Computing (MEDICON'2016),vol. 57, pp 114-118, Cyprus, 2016.



Gören S., Gursoy C.C., Yildiz A., "Speeding Up Logic Locking via Fault Emulation and Dynamic Multiple Fault Injection," Journal of Electronic Testing: Theory and Applications (JETTA), vol. 31, pp. 525-536, Springer, 2015.

Gener Y.S., Yildiz A., Gören S., "Low-Cost and Low-Power Video Filtering with Parallel Many Cores," International Conference on Electrical and Electronics Engineering (ELECO'2015), Bursa, 2015.

Canbay F., Levent V.E., Serbes G., Ugurdag, H.F., Gören S., Aydın N. "An area efficient real time implementation of dual tree complex wavelet transform in field programmable gate arrays," 15th IEEE International Conference on Bioinformatics and Bioengineering (BIBE'2015), Belgrade, Serbia, 2015.

Canbay F., Levent V.E., Serbes G., Aydın N., Gören S., "Field Programmable Gate Arrays Implementation of Dual Tree Complex Wavelet Transform," 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC'2015), Milan, Italy, 2015.



Yuce B., Ugurdag H.F., Gören S., Dundar G., "Fast and Efficient Circuit Topologies for Finding the Maximum of n k-bit Numbers," IEEE Transactions on Computers, vol. 63, no. 8, pp. 1868-81, 2014.

Türk,Y., Demir, O., Gören S., “Real Time Wireless Packet Monitoring with Raspberry Pi Sniffer,” International Symposium on Computer and Information Sciences (ISCIS'2014), Krakow, Poland, 2014.

Türk,Y., Demir, O., Gören S., “Dusuk Maliyetli 802.11 Kablosuz Ag Dinleyici,” Elektrik- Elektronik, Bilgisayar ve Biyomedikal Mühendisligi Sempozyumu (ELECO’2014), Bursa, 2014.

Johnson A., Saha S., Chakraborty R.S., Mukhopadhyay D., Gören S., "Fault Attack on AES via Hardware Trojan Insertion by Dynamic Partial Reconfiguration of FPGA over Ethernet" 9th Workshop on Embedded Systems Security (WESS 2014 (A Workshop of the Embedded Systems Week (ESWEEK'2014)), New Delhi, India, October 17, 2014.



Gök M. Y., Sagiroglu M.S., Unsalan C. and Gören S., "Programmable Hardware based Short Read Aligner Using Phred Quality Scores," ASE/IEEE International Conference on BioMedical Computing, Washington DC, USA, 2013.

Ugurdag H.F., Temizkan F., Gören S.,“Generating Fast Logic Circuits for m-select n-port Round Robin Arbitration,” 21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'2013), Istanbul, Turkey, October 2013.

Canbay F., Serbes G., Gören S., Aydın N., “Çift-ağaç Karmaşık Dalgacık Dönüşümü’nün Gerçek Zamanlı Gerçekleştirimi”, Otomatik Kontrol Ulusal Toplantısı (TOK’2013), Malatya, 2013.

Gök M.Y., Sagiroglu M.S., Unsalan C., Gören S., "Reconfigurable Hardware-based Genome Aligner Using Quality Scores,” IEEE Signal Processing and Communications Applications Conference (SIU'2013), North Cyprus, April, 2013.

Yuce B., Ugurdag H.F., Gören S., Dundar G., "A Fast Circuit Topology for Finding the Maximum of n k-bit Numbers," IEEE Symposium on Computer Arithmetic (ARITH'2013), Austin, TX, April 7-10, 2013.

Gören S., Turk Y., Ozkurt O., Yildiz A., Ugurdag H.F., "Achieving Modular Dynamic Partial Reconfiguration with Difference-Based Flow," 21st ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA'2013), Monterey, CA, USA, February 11-13, 2013.

Gören S., Ozkurt O., Yildiz A., Ugurdag H.F., Chakraborty R.S., Mukhopadhyay D., "Partial Bitstream Protection for Low-Cost FPGAs with Physical Unclonable Function, Obfuscation, and Dynamic Partial Self Reconfiguration," Computers and Electrical Engineering, Elsevier, vol. 39, no. 2, 2013.



Gören S., Ozkurt O., Turk Y., Yildiz A., Ugurdag H.F., "Enabling Difference-Based Dynamic Partial Self Reconfiguration for Large Differences," IEEE International Design and Test Symposium, Doha, Qatar, December 15-17, 2012.

Ugurdag H.F., Basaran A., Akdogan T., Guney V.U., Gören S., "FPGA based Particle Identification in High Energy Physics Experiments," IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'2012), Delft, Netherlands, July 2012.

Basaran A., Ugurdag H.F., Akdogan T., Guney V.U., Gören S., "Ultra-Fast Curve Fitting for Pulses on FPGA," IEEE Signal Processing and Communications Applications Conference (SIU'2012), Mugla, Turkey, April 2012.



Gören S., Ugurdag H.F., Palaz O.,

ACM DL Author-ize serviceDefect-Aware Nanocrossbar Logic Mapping through Matrix Canonization Using Two-Dimensional Radix Sort
ACM Journal on Emerging Technologies in Computing Systems (JETC), vol.7, no. 3, 2011

Gören S., Yildiz A., Ozkurt O., Ugurdag H.F., "FPGA Bitstream Protection with PUFs, Obfuscation and Multi-boot," International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'2011), Montpellier, France, June 2011.



Gören S., Ugurdag H.F., Palaz O., "Defect-Tolerant Logic Mapping for Nanocrossbars Based on Two-Dimensional Sort," International Symposium on Computer and Information Sciences. Lecture Notes in Electrical Engineering 62 , pp. 399-404, 2010.

Ugurdag H.F., Gören S., Canbay F., "Gravitational Pose Estimation," Computers and Electrical Engineering, Elsevier, vol. 36, pp. 1165-1180, 2010. DOWNLOAD GPE SOFTWARE

Gören S., Ugurdag H.F., Yildiz A., Ozkurt O.,"FPGA Design Security with Time Division Multiplexed PUFs," International Conference on High Performance Computing & Simulation (HPCS'2010), Caen, France, July 2010.

Gören S., Ugurdag H.F., Palaz O., "Defect-Aware Nanocrossbar Logic Mapping using Bipartite Subgraph Isomorphism & Canonization," 15th IEEE European Test Symposium (ETS'10), Prague, Czech Republic, May 2010.

Gören S., Ugurdag H.F., Ozkurt O., Yildiz A. "PUF, DPSR ve Bulandirma Yoluyla Sayisal Yongalarin Güvenilir Yapilmasi," EMO 3. AG VE BILGI GUVENLIGI ULUSAL SEMPOZYUMU, Ankara, Turkey, Feb. 2010. (in Turkish)



Ugurdag H.F., Argali E., Eker O.E., Basaran A., Gören S. and Ozcan H. "Smart Question (sQ): Tool for Generating Multiple-Choice Test Questions," Proceedings of WSEAS International Conference on Education and Educational Technology (EDU'09), Genoa, Italy, October 2009.

Ileri F., Gören S., and Ugurdag H.F. "Virtual Smart Board," Proceedings of WSEAS International Conference on Education and Educational Technology (EDU'09), Genoa, Italy, October 2009.

Gören S., "Optimization of embedded controllers based on redundant transition removal and fault simulation using k-wise tests," Journal of Circuits, Systems, and Computers, vol. 18, no. 4, pp. 647-663, 2009.



Uğurdağ H.F., Gören S., Canbay F., "Correspondenceless Pose Estimation from a Single 2D Image using Classical Mechanics," IEEE International Symposium on Computer and Information Sciences, October 2008, Turkey.

Gören S., "A Meta-heuristic for Shared BDD Minimization," VLSI-SOC 16th IFIP/IEEE International Conference on Very Large Scale Integration, October 15-18 2008, Greece.

Gören S., Karahoca A., Onat F. Y. and Gören M.Z, "Prediction of cyclosporine A blood levels: an application of the adaptive-network-based fuzzy inference system (ANFIS) in assisting drug therapy," European Journal of Clinical Pharmacology, vol. 64, no. 8, pp. 807-814, 2008.



Gören S., "Optimization of Interacting Controllers Using K-wise Tests," International Design and Test Workshop, pp. 169-174, Cairo, Egypt, December 2007.

Gören M.Z., S. Gören, A. Karahoca, and F.Y. Onat, "Terapötik İlaç Düzeyi İzlemi Verilerine Veri Madenciliği Tekniklerinin Uygulanması İle Siklosporin A Kan Düzeylerinin Önceden Tahmini," Türk Farmakoloji Derneği 19. Ulusal Farmakoloji Kongresi, pp. 341-2, Trabzon, Ekim 2007.

Gören, S., F.J. Ferguson, "On state reduction of incompletely specified finite state machines," Computers and Electrical Engineering, Elsevier, vol. 33, no. 1, pp. 58-69, January 2007.



Gören, S., F.J. Ferguson,

ACM DL Author-ize serviceTest sequence generation for controller verification and test with high coverage
ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 11, no. 4, 2006.

Uğurdağ H.F., Y. Şahin, O. Başkirt, S. Dedeoğlu, S. Gören, Y.S. Koçak, "Population-based FPGA Solution to Mastermind Game," 1st NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pp. 237-246, Istanbul, Turkey, June 2006.



Gören, S., F.J. Ferguson, "Testing Finite State Machines Based On a Structural Coverage Metric," IEEE International Test Conference, pp. 773-780, Baltimore, Maryland, October 2002.

Gören S., F.J. Ferguson, "CHESMIN: A Heuristic for State Reduction of Incompletely Specified Finite State Machines," IEEE/ACM Design Automation and Test in Europe, pp. 248-254, Paris, France, March 2002.



Gören, S., F.J. Ferguson, "Checking Sequence Generation for Asynchronous Sequential Elements," International Test Conference, pp. 406-413, September 1999.

Chen, P., S. Gören et al., "Reducing Compilation Time of Zhong's FPGA-based SAT solver," IEEE Symposium on FPGAs for Custom Computing Machines, pp. 308-309, April 1999.



Gören, S. et al., "Novel VLSI architectures for morphological filtering," IEEE Workshop on Nonlinear Image and Signal Processing, pp. 875-878, Neos Marmara, Greece, June 1995.

Gören S., S. Balkır, G. Dündar, and E. Anarım, "Novel VLSI architectures for morphological filtering," Proceedings of SIU'95, Nevşehir, Türkiye, Book A. Image Processing, pp. 187-192, April 26-28, 1995 (in Turkish).



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